In order to protect the security of network data, a high speed chip modulefor encrypting and decrypting of network data packet is designed. The chipmodule is oriented for internet information security SOC (System on Chip)design. During the design process, AES (Advanced Encryption Standard) and 3DES(Data Encryption Standard) encryption algorithm are adopted to protect thesecurity of network data. The following points are focused: (1) The SOC (Systemon Chip) design methodology based on IP (Intellectual Property) core is used.AES (Advanced Encryption Standard) and 3DES (Data Encryption Standard) IP(Intellectual Property) cores are embedded in the chip module, peripheralcontrol sub-modules are designed to control the encryption-decryption module,which is capable of shortening the design period of the chip module. (2) Theimplementation of encryption-decryption with hardware was presented, whichimproves the safety of data through the encryption-decryption chip and reducethe load of CPU. (3) In our hardware solution, two AES (Advanced EncryptionStandard) cores are used to work in parallel, which improves the speed of theencryption module. Moreover, the key length of AES (Advanced EncryptionStandard) encryption algorithm is designed with three optional configurationsat 128 bits, 256 bits and 192 bits respectively and six optional encryptionalgorithm modes: CBC (Cipher Block Chaining) mode, ECB (Electronic Code Book)mode, GCM (Galois/Counter Mode) mode, XTS(cipherteXT Stealing) mode, CTR(CounTeR) mode and 3DES respectively, which adds the flexibility to itsapplications.
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